Stackup Beware: Case Study of the Effects on Transmission Line Losses Due to Mixed Reference Plane Roughness

Conductor surface roughness has traditionally been applied to copper foil to promote adhesion to the dielectric material. Early PCBs were constructed with only single or double-sided copper core laminates. The one important metric for copper was its purity and the roughness to improve peel strength. There was no such thing as a PCB stackup, and no one worried about impedance or transmission line losses.

然而,多年来,多氯联苯演变成μlti-layer constructions with increased attention paid to impedance control and transmission line losses. Thus, a PCB stackup definition is now vital for consistent performance.

For any construction project, a blueprint is needed before building begins. Similarly for PCBs, a stackup drawing and detailed fabrication notes are required. Part of the stackup design process includes signal integrity (SI) modeling for characteristic impedance and transmission loss. If a design is running at 56 Gb/s pulse amplitude modulation level 4 (PAM-4), for example, low loss dielectrics and low roughness copper for the signal traces are likely required.

Sometimes overlooked in the stackup is the roughness of the reference planes. Often thin core laminate power and ground (GND) planes will specify reverse-treated foils (RTF), which are rougher on the side that bonds to the prepreg. Sometimes one of these planes, usually GND, acts as a reference plane to an adjacent signal layer as shown in Figure 1. If that adjacent high-speed signal layer is using smoother copper than one or both reference planes, a higher insertion loss than expected for that layer will occur.

Fig. 1 A stripline cross-section from a stackup showing a thin core laminate (top) with RTF bonded to prepreg adjacent to a high-speed differential pair with smooth foil.

A similar scenario could occur for high density interconnect or HDI technology. This is a popular method to increase component density on modern PCBs. By the nature of the stackup construction, a rougher copper reference plane could sometimes also end up adjacent to a signal layer as well. Thus, if insertion loss is a concern, copper foil roughness of reference planes must be considered.

How is this known before the design stackup and first prototype build? With no empirical data to go by, heuristic, high-level design (HLD) modeling methods are relied on, starting with published parameters found solely in manufacturer’s data sheets. Heuristic HLD modeling is a practical technique that is not guaranteed to be perfect; but, it is still adequate to determine a satisfactory solution sooner, rather than later.

For dielectric parameters, choose a dielectric constant (Dk) and dissipation factor (Df) at or near the Nyquist frequency of the baud rate, then determine the effective Dk (Dkeff) due to roughness.²where:

H is the thickness of core/prepreg, Rz is surface roughness of copper, and Dk is the published value in laminate suppliers’ Dk/Df tables. Equation (1) assumes Rz of the foil on each side of the dielectric (core or prepreg) is the same.

For conductor loss, use Rz roughness numbers from copper suppliers’ data sheets and oxide/oxide alternative (OA) Rz roughness numbers from your favorite fab shop, then apply the Cannonball-Huray roughness model.^{1, 3, 4}

Cannonball-Huray Model

The original Huray model is defined as:

The Cannonball-Huray model allows extraction of the right parameters using Rz roughness for the core and prepreg sides of the foil.¹Because the Cannonball-Huray model assumes the ratio of A_matte/A_flat= 1, and N_i= 14 spheres, the radius of a sphere (r) can be determined by:

and area of a flat tile base (A_flat) is determined by:

Wildriver Isola I-Tera® MT40 Custom Modeling Platform Case Study

To study the effect of reference plane roughness on transmission insertion loss, Wildriver Technology’s custom modeling platform (CMP),⁵shown in Figure 2, is used as a case study. This CMP was custom developed for Isola⁶to characterize their new I-Tera MT40 very low loss laminate material.

It combines 27 structures based on a consistent development of primitive structures and is useful for performing a host of calibrations including automatic fixture removal, unknown THRU, WinCal XE™ calibration, and VNA gating and time transform analysis.

Fig. 2 Wildriver Isola I-Tera MT40 Custom Modeling Platform. (Source: Wildriver Technology)⁵

Stackup Validation

PCB分层盘旋飞行是如图3所示。经常PCB足总b shop field application engineers modify existing stackups and unintentionally make errors in transferring new parameters from data sheets into their software tools; also, they may not necessarily know the design intent of the stackup. The first step for any model correlation exercise, therefore, is to sanitize the stackup to ensure it meets the product design intent for SI performance. In fact, that is how the issue of different plane roughness was uncovered.

Since it is good practice to specify the same roughness for both the reference planes and the adjacent signal layers, it was incorrectly assumed that this was the case for any high-speed stackup; however, Layers E1, E2 and E7, E8 specify 1 oz RTF, while layers E3, E4 and E5, E6 specify 1 oz VLP2 foil. Because the Isola I-Tera MT40 CMP is intended to aid in modeling test structures, this is not a fatal flaw. On the contrary, it is a perfect platform to assess the effect of rougher reference planes.

Fig. 3 Isola I-Tera MT40 Custom Modeling Platform stackup. (Source: Wildriver Technology)⁵

进一步检查发现核心分层between E3, E4 and E5, E6 specify 1067/2x3313 glass styles, but this combination is not listed for 12 mil thickness. Instead, only 3x3313 core material is offered. Because of that, the Dk shown is also wrong and affects the impedance of the traces. The right Dk for 3 x 3313 is 3.53, not 3.33.

Foil Roughness

As previously mentioned, foil roughness affects the effective Dk, so the right number must be used for model validation. The standard VLP2 foil, used on I-Tera MT40 core laminates is BF-TZA foil. Optional RTF foil, used for layers E1, E2 and E7, E8, is TWLS-B. (Both are available from Circuit Foil.⁷)

Relevant roughness parameters are shown in Figure 4. For the core side of the foil, the Rz parameters for the treated side are listed; but, there are two Rz parameters, JIS B 601 and ISO 4287. Which one is appropriate for modeling?

IPC-TM-650 Section 1.2⁸states,“The foil profile of foils shall be evaluated using the parameter Rz (DIN) or RTM, which is defined as the average maximum peak to valley height of five consecutive sampling lengths within the measurement length. This value is approximately equivalent to the values of profile determined from microsectioning techniques.” Section 1.3 states further, “RZ (ISO) is a different parameter from Rz (DIN) and is not applicable to this method.”

Rz JIS represents the 10-point mean value, which is the sum of the average of the five highest peaks and the five lowest valleys over the sample length. Rz DIN is similar; except it is defined as the average maximum peak to valley height of five consecutive sampling lengths within the measurement length. Thus Rz JIS is used for modeling analysis.

Fig. 4 Roughness parameters from Circuit Foil data sheets:⁷VLP2 standard foil used on I-Tera MT40 (a), RTF option used for relevant layers in the stackup (b).

Determining Effective Dk Due to Roughness

The first step in HLD impedance modeling is to gather all the dielectric and foil data sheet parameters to determine the effective Dk. Figure 5 shows the core thickness, prepreg and signal traces from the stackup geometry in Figure 3. Note that photos are for illustrative purposes only and are not actual cross-sections from the CMP PCB. Dk for the core and prepreg were obtained from Isola I-Tera MT40 Dk/Df tables.⁶

Fig. 5 Data sheet parameters for RTF/VLP2 foil roughness and dielectric properties for the I-Tera MT40 stackup geometry. (Surface roughness pictures source: Circuit Foil)⁷

The top reference plane is TWLS-B RTF foil with matte sideJIS, obtained from the Circuit Foil data sheet (see Figure 4). The roughness surface profile is shown in the upper left. After OA smoothing,

BF-TZA foil is used for both sides of the core laminate. The top surface of the stripline trace, shown in the upper right picture, is the drum side of the foil before OA treatment. After OA treatment, Rz2 ~ 1.9 μm.¹

The bottom surface profile of the stripline trace and the top surface of the bottom reference plane are the treated matte sides of the foil, shown in the bottom right and bottom left of Figure 5, respectively. They both share the same roughness (Rz3, Rz4 =2.5μm JIS) from the BF-TZA data sheet (see Figure 4).

The next step is to convert the imperial thickness units to metric, then use Equation (1) to determine Dkeff due to roughness for the prepreg and core.

Determine Cannonball-Huray Roughness Parameters

Several popular electronic design automation tools include the Cannonball-Huray model directly as an option, so the respective Rz parameter is all that is needed.

Any of these tools can be used for HLD modeling, but my favorite is Polar SI9000⁹because of its simplicity and sufficient accuracy for prefabrication modeling and analysis. Many fab shops use this tool for impedance prediction, so it is easy to coordinate with them during the HLD stage of a project. Plus, it has the added benefit of modeling transmission loss and exporting S-parameters in touchstone format for further channel modeling in other tools.

Because Polar Si9000 assumes all the reference planes have the same roughness, it only allows Rz roughness parameters to be inputted for the matte and drum side of the signal trace. The best that one can do, is take the average roughness of Rz1, Rz2 and Rz3, Rz4:

Simulation Correlation

When Dkeff due to roughness values is used instead of published Dk values, the new impedance prediction is 48.24 ohms (see Figure 6).

Fig. 6 Polar Si9000 impedance prediction with Dkeff due to roughness.

Dkeff/Df for H1, H2 is then input into the causal dielectric model at 10 GHz (see Figure 7a), while Rz_matte, Rz_drumis inputted into the Cannonball-Huray model (see Figure 7b).

Fig. 7 Causal Dkeff/Df dielectric (a) and Cannonball-Huray roughness model (b) input panels in Polar Si9000.

After a 6-inch transmission line is simulated, the S-parameters are exported in touchstone format. Keysight Pathwave ADS¹⁰is used for further processing and analysis.

图8比较模拟插入损耗与de-embedded reflectionless generalized modal (GM) S-parameter measurements, provided by Wildriver Technology.⁵Excellent correlation is observedwithout fittingto measured data!

Fig. 8 HLD insertion loss simulation correlation with measured data for an as-designed stackup from data sheet and stackup parameters.

Figure 9 plots simulated Dkeff versus measurements. At 10 GHz, simulated Dkeff is 0.105 (2.8 percent) lower than the measured value. Without actual cross-section microscopic measurements, it is difficult to conclude if the published Dk is wrong, or if there is process variation with roughness parameters used in the model.

It is interesting to note that measured Dkeff is not a constant value over frequency, as shown in the I-Tera MT-40 Dk/Df tables. Instead, Figure 9 shows that it varies over frequency; so, the Dk/Df data sheet numbers are suspect. Regardless, for the HLD modeling process, the simulation results are within an acceptable tolerance.

Fig. 9 HLD Dkeff simulation correlation for as designed stackup.

Exploring the Effects of Alternate Foil Roughness

With good correlation to measurements, the HLD modeling process is repeated to explore different foil roughness options. Figure 10 summarizes the thickness of core, prepreg and signal trace for VLP2/VLP2 foil (see Figure 10a) and VLP1/VLP1 foil (see Figure 10b). Note that photos are for illustrative purposes only and are not actual cross-sections from the CMP PCB. Respective Dkeff, and Cannonball-Huray roughness parameters are recalculated using the same steps as VLP2/RTF case above.

Fig. 10 Alternate foil options simulated for what-if loss comparison: VLP2/VLP2 foil parameters for all copper layers (a) VLP1/VLP1 foil parameters for all copper layers (b). (Surface roughness pictures source: Circuit Foil)⁷

Figure 11 shows the simulation results of all three scenarios. As expected, when the reference plane foil roughness goes from RTF/VLP2 to VLP2/VLP2 there is improvement in insertion loss (see Figure 11a). At 14 GHz the improvement is 0.5 dB and at 28 GHz it is 1 dB.

When VLP1/VLP1 foil is used, there is further improvement (0.8 dB at 14 GHz and 1.7 dB at 28 GHz). For a loss sensitive design, therefore, one might want to consider the VLP1 foil option.

When Dkeff plots are compared, effective Dk approaches actual Dk/Df data sheet values in the tables when smoother copper is used, as expected (see Figure 11b).²Since Dkeff is derived by phase delay, propagation delay is affected by rougher copper.

Fig. 11 What-if simulation comparison of VLP2/RTF, VLP2/VLP2, VLP1/VLP1 foil options and their effect on insertion loss (a) and Dkeff (b).

Conclusions

Roughness of reference planes make a significant difference in loss and phase delay, especially if one of the reference planes is RTF. If loss is important, then all high-speed reference planes should have the same foil roughness specified.

The heuristic HLD modeling method is a useful and accurate way to determine prefabrication impedance and loss predictions using data sheet parameters.

From the analysis and measurements conducted for this case study, it is found that published Dk from I-Tera MT40 Dk/Df tables is not a flat constant over frequency, and it is confirmed that Rz JIS is the right parameter to use from the Circuit Foil data sheet, instead of Rz ISO.

Acknowledgments

The author would like to thank Al Neves, CTO Wildriver Technology, for providing the custom modeling platform design details and measured data for this case study. He would also like to thank Michael Gay, Director Business Development – Strategic Accounts at Isola Group, for providing foil supplier’s data sheets used on I-Tera MT40 laminates.

References

1. B. Simonovich, Heuristic Modeling of Transmission Lines due to Mixed Reference Plane Foil Roughness in Printed Circuit Board Stackups, White Paper, Lamsim Enterprises Inc., June 2021. Web.http://lamsimenterprises.com/Heuristic%20Modeling%20of%20Transmission%20Lines%20due%20to%20Mixed%20Reference%20Plane%20Foil%20Roughness.pdf.
2. B. Simonovich, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness,” DesignCon Proceedings, February 2017.
3. B. Simonovich, Practical Method for Modeling Conductor Surface Roughness Using the Cannonball Stack Principle, White Paper Issue 2, Lamsim Enterprises Inc., April 2015. Web.http://lamsimenterprises.com/White_Paper-Practical_Method_for_Modeling_Conductor_Surface_Roughness_Using_The_Cannonball_Stack-Principle-v2.0.pdf.
4. L. Simonovich, “Practical Method for Modeling Conductor Roughness Using Cubic Close-Packing of Equal Spheres,” IEEE International Symposium on Electromagnetic Compatibility, July 2016, pp. 917-920.
5. Wild River Technology LLC, 8311SW Charlotte Drive Beaverton, OR 97007. Web.https://wildrivertech.com/.
6. Isola Group S.a.r.l., 3100 West Ray Road, Suite 301, Chandler, AZ 85226. Web.http://www.isola-group.com/.
7. Circuit Foil, 6 Salzbaach, 9559 Wiltz, Grand Duchy of Luxembourg. Web.https://www.circuitfoil.com/portfolio/.
8. IPC-TM-650 Test Methods Manual 2.2.17 A, Surface Roughness and Profile of Metallic Foils (Contacting Stylus Technique), IPC, February 2001.
9. Polar Instruments Si9000e [computer software] Version 2018. Web.https://www.polarinstruments.com/index.html.
10. Keysight Pathwave Advanced Design System (ADS) [computer software], (Version 2021 update2). Web.http://www.keysight.com/en/pc-1297113/advanced-design-system-ads?cc=US&lc=eng.